1. Field of the Invention
The present invention relates to an apparatus and a method for amplifying power in a wireless communication system. More particularly, the present invention relates to an apparatus and a method for a power amplification of high efficiency and high linearity using an error amplifier.
2. Description of the Related Art
In a wireless communication system, a Power Amplifier (PA) is a very important component. The PA must satisfy various different criteria such as operating at high efficiency, supporting a broad band signal and providing high power, all while maintaining a reasonable cost. Hence, a great deal of research is being conducted to develop such a PA. However, it is not easy to satisfy all of the requirements of high efficiency, broad band support and high power. Recently, an Envelope Tracking (ET) technique and an Envelope Elimination and Restoring (EER) technique, which are more efficient than a conventional Linear amplification using Nonlinear Components (LINC) technique or a Doherty technique, are being adopted.
FIG. 1 illustrates a conventional PA in the EER structure.
Referring to FIG. 1, an input Radio Frequency (RF) signal is split into an amplitude component and a phase component and is then amplified. After the input RF signal is split, an amplitude detector 100 detects the amplitude component from the RF signal and outputs an envelope signal. Similarly, a phase detector 102 detects the phase component from the RF signal and outputs a phase signal. An envelope amplifier 104 amplifies the envelope signal fed from the amplitude detector 100 and outputs the amplified envelope signal to a switching mode PA 106. That is, a drain bias of the switching mode PA 106 for amplifying the phase signal is supplied from the envelope amplifier 104. Hence, when the PA 106 operates in a saturation mode, the envelope of the output signal from the PA 106 is controlled by the output waveform of the envelope amplifier 104.
In general, the envelope amplifier 104 includes a high-efficiency switching amplifier and a broadband voltage amplifier. Since 80˜85% of the envelope signal power of an Orthogonal Frequency Division Multiplexing (OFDM) signal ranges in a low frequency (below 1 MHz), the efficiency of the switching amplifier considerably affects the efficiency of the entire system. The switching amplifier can acquire an efficiency of over 80% by employing a Class-S amplifier similar to a DC-DC buck converter. However, the broadband characteristic, which is obtained from the PA, deteriorates for an input signal of a high Peak to Average Power Ratio (PAPR). This is a decisive factor on the efficiency of the entire system as well.
In the power amplification of the EER structure, the overall efficiency is determined by multiplying the efficiency of the envelope amplifier 104 by the efficiency of the PA 106. Since the efficiency of the PA 106 cannot be optimized for every drain voltage, the design seeks to provide the highest efficiency around the average power. Accordingly, the average efficiency of the PA 106 does not reach the maximum efficiency. Furthermore, this EER structure has many shortcomings in view of linearity, particularly in the low envelope voltage. Thus, the PA of the EER structure should be used together with a Digital Pre-Distortion (DPD) technique. An EER structure using Delta Sigma Modulation (DSM), which is advantageous in terms of the efficiency and the linearity, is explained with reference to FIG. 2.
FIG. 2 illustrates a conventional PA transmitter having an EER structure using DSM.
Referring to FIG. 2, A Field-Programmable Gate Array (FPGA) 200 separates an envelope signal and a phase signal from an RF signal.
A delta-sigma modulator 210 delta-modulates the envelope signal output from the FPGA 200 to a digital signal. In more detail, the delta-sigma modulator 210 approximately predicts a value of the envelope signal, computes an error, and corrects the error using the accumulated error. The output signal quantized at a quantizer 214 is fed back to make a difference from the envelope signal in step 215. The output signal integrated at an integrator 212 is fed back and accumulated in step 216. By continually integrating the difference between the input signal and the feedback signal at the integrator 212, the signals themselves are integrated in the end. Its result is quantized through the quantizer 214.
A switch 230 performs a switching operation using the constant envelope signal quantized at the delta-sigma modulator 210 and supplies the drain voltage of a switching mode PA 240.
The switching mode PA 240 amplifies the phase signal output from the FPGA 200 using the switching control signal fed from the switch 230.
With respect to the signal output from the switching mode PA 240, a Band-Pass Filter (BPF) 250 passes signals in a specific frequency range and rejects signals outside the range.
Since the output signal of the delta-sigma modulator 210 has a constant envelope, the switching mode PA 240 can be designed to exhibit maximum efficiency. The switching mode PA 240 is switched on and off by the output signal from the delta-sigma modulator 210. Accordingly, the switching mode PA 240 is designed to produce voltage of the highest efficiency during the switch-on. However, while this design is advantageous in terms of the efficiency, it is difficult to extend the bandwidth because of the slow switching speed at high power.
As discussed above, the PA transmitter having the general EER structure additionally requires a compensation scheme such as DPD, because of concerns with linearity, and suffers limitations in enhancing the efficiency when the PAPR is high. However, in the EER structure based on the DSM, which mends the drawbacks of the general EER structure, it is difficult to extend the bandwidth because of the switching frequency limitation of the element. As a result, quantization noise is increased.